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Electronic Design
PCB proofing high-speed PCB anti-interference design based on DSP
Electronic Design
PCB proofing high-speed PCB anti-interference design based on DSP

PCB proofing high-speed PCB anti-interference design based on DSP


pcb proofing 1 DSP system interference generation analysis In order to make a stable and reliable DSP system, interference must be eliminated from all aspects, even if it cannot be completely eliminated, it must be minimized as much as possible. For DSP systems, the main interference comes from the following aspects: ① Input and output channel interference. Refers to interference entering the system through the forward channel and the backward channel, such as the data acquisition link of a DSP system. The interference is superimposed on the signal through the sensor, which increases the error of data acquisition. In the output link, interference can increase the output data error, or even make a complete error, causing the system to crash. Optocoupler devices can be reasonably used to reduce the interference of input and output channels, and the interference of the sensor and the DSP main system can be used to electrically isolate the interference. ② Interference of the power supply system. The main source of interference for the entire DSP system. The power supply adds its noise to the power supply while providing power to the system. The power supply line must be decoupled during the circuit design of the power supply chip. ③ Space radiation coupling interference. The coupling through radiation is usually called crosstalk. Crosstalk occurs in the electromagnetic field generated when current flows through the wires, and the electromagnetic field induces transient currents in adjacent wires, causing nearby signals to be distorted or even errors. The strength of crosstalk depends on the geometrical size and separation distance of devices and wires. In DSP wiring, the larger the signal line spacing and the closer to the ground line, the more effective it is to reduce crosstalk. 2 Design the PCB for the cause of the interference. The following shows how to reduce various interferences in the PCB production process of the DSP system.

pcb proofing 1 DSP system

           In order to improve the signal quality, reduce the difficulty of wiring, and increase the EMC of the system, in the DSP high-speed digital circuit of the laminated design of the multi-layer board of the pcb proofing, the laminated design of the multi-layer board is generally adopted. The stacked design can provide the shortest return path, reduce the coupling area, and suppress differential mode interference. In the stacked design, the distribution of dedicated power layer and ground layer, and the tight coupling of the ground layer and the power layer is good for suppressing common mode interference (using adjacent planes to reduce the AC impedance of the power plane). Take the 4-layer board shown in Figure 1 as an example to illustrate the laminated design. There are many advantages to adopting this 4-layer PCB design structure. There is a power layer under the top layer, and the power pins of the components can be directly connected to the power supply without passing through the ground plane. The key signal is selected on the bottom layer (bottorn layer), so that the important signal wiring space is larger, and the devices are placed on the same layer as much as possible. If it is not necessary, do not make a two-layer part board, which will increase assembly time and assembly complexity. Such as the top layer, only when the top layer components are too dense, the height is limited and low heat generation devices, such as decoupling capacitors (patch) are placed on the bottom layer. For the DSP system, there may be a large number of wires to be routed, and the layered design is adopted, and the wires can be routed in the inner layer. If a lot of valuable wiring space is wasted according to the traditional through holes, blind/buried vias can be used to increase the wiring area.
           PCB Proofing Layout Design In order to get the best performance of the DSP system, the layout of the components is very important. Place DSP, Flash, SRAM, and CPLD devices first, carefully consider the wiring space, then place other ICs according to the principle of functional independence, and finally consider the placement of I/O ports. Combine the above layout and consider the PCB size: if the size is too large, the printed lines will be too long, the impedance will increase, the noise resistance will be reduced, and the board cost will increase; if the PCB is too small, the heat dissipation will not be good, and the space will be limited , Adjacent lines are easily disturbed. Therefore, the device should be selected according to actual needs, combined with the wiring space, and roughly calculate the size of the PCB. When laying out the DSP system, pay special attention to the placement of the following devices.
(1) High-speed signal layout In the entire DSP system, the main high-speed digital signal lines are between DSP and Flash and SRAM, so the distance between devices should be as close as possible, and their connections should be as short as possible, and they should be connected directly. Therefore, in order to reduce the influence of transmission lines on signal quality, high-speed signal traces should be as short as possible. Also consider that many DSP chips with speeds up to several hundred MHz require a snake-shaped winding (delay tune). This will be emphasized in the wiring below.
(2) The layout of digital-analog devices is mostly not a single functional circuit in a DSP system. A large number of digital devices and digital-analog hybrid devices of CMOS are used, so the digital/analog layout should be separated. The analog signal devices are concentrated as much as possible, so that the analog ground can draw an independent area belonging to the analog signal in the middle of the entire digital ground, so as to avoid the interference of the digital signal to the analog signal. For some digital-analog hybrid devices, such as D/A converters, they are traditionally regarded as analog devices, placed on the analog ground, and provided with a digital loop to allow digital noise to be fed back to the signal source to reduce digital noise The impact on the analog ground.
(3) The layout of the clock As far as possible from the clock, chip selection and bus signals, the I/O lines and connectors should be kept as far away as possible. The clock input of the DSP system is very susceptible to interference, and its processing is very critical. Always ensure that the clock generator is as close to the DSP chip as possible, and make the clock line as short as possible. The outer shell of the clock crystal oscillator is preferably grounded.
(4) Decoupling layout In order to reduce the instantaneous overshoot of the voltage on the power supply of the integrated circuit chip, a decoupling capacitor is added to the integrated circuit chip, which can effectively remove the influence of the burr on the power supply and reduce the power loop reflection on the PCB . Adding a decoupling capacitor can bypass the high frequency noise of the integrated circuit device, and can also be used as an energy storage capacitor to provide and absorb the instantaneous charging and discharging energy of the integrated circuit door opening and closing.
           For pcb proofing in the DSP system, place decoupling capacitors for each integrated circuit, such as DSP, SRAM, Flash, etc., and add them between each power supply and ground of the chip, and pay special attention to the decoupling capacitors as close as possible to the power supply terminal (source) and IC component pins (pin). Ensure the purity of the current from the power supply terminal (sotlrce terminal) and the IC, and shorten the noise path as much as possible. As shown in Figure 2, when handling capacitors, use large vias or multiple vias, and the wiring between vias and capacitors should be as short and thick as possible. When the distance between the two vias is too long, it is not good because the path is too large; the best is that the two vias of the decoupling capacitor are as close as possible, so that the noise can reach the ground in the shortest path.