PCB Tech - Non-isolated switching power supply PCB layout

A common problem with switching power supplies is "unstable" switching waveforms. Sometimes, the jitter is in the sound section and the magnetic component will produce audio noise. If the problem lies in the layout of the printed circuit board, it may be difficult to find the cause. The correct PCB layout at the initial stage of the switching power supply design is very critical.

The power supply designer must have a good understanding of the technical details and the functional requirements of the final product. Therefore, from the beginning of the circuit board design project, the source designer should cooperate closely with the PCB layout designer on the key electrical layout.

A good layout design can optimize power efficiency and reduce thermal stress; more importantly, it minimizes noise and the interaction between traces and components. To achieve these goals, the designer must understand the current conduction path and signal flow inside the switching power supply. To realize the correct layout design of non-isolated switching power supply, the following design elements must be kept in mind.

2. Layout planning

For the embedded dc/dc power supply on a large circuit board, in order to obtain the best voltage regulation, load transient response and system efficiency, it is necessary to make the power output close to the load device and minimize the interconnection impedance and conduction on the PCB trace. Pressure drop. Ensure that there is a good air flow to limit thermal stress; if forced air cooling measures can be used, the power supply should be close to the fan.

In addition, large passive components (such as inductors and electrolytic capacitors) must not block airflow through low-profile surface-mounted semiconductor components, such as power MOSFETs or PWM controllers. To prevent switching noise from interfering with the analog signals in the system, you should avoid placing sensitive signal lines under the power supply as much as possible; otherwise, you need to place an internal ground layer between the power layer and the small signal layer for shielding.

The key is to plan the location of the power supply and the demand for board space in the early design and planning stages of the system. Sometimes designers ignore this advice and focus on the more "important" or "exciting" circuits on the large system board. Power management is regarded as an afterthought, and the power is placed on the extra space on the circuit board. This approach is very detrimental to high-efficiency and reliable power supply design.

For multilayer boards, a good method is to place a DC ground or DC input/output voltage layer between the high-current power component layer and the sensitive small signal trace layer. The ground layer or DC voltage layer provides an AC ground shielding small signal traces to prevent interference from high-noise power traces and power components.

As a general rule, neither the ground plane nor the DC voltage plane of a multilayer PCB should be separated. If this separation is unavoidable, try to reduce the number and length of the traces on these layers, and the layout of the traces should be kept in the same direction as the high current to minimize the impact.

3. Layout of the power stage

The switching power supply circuit can be divided into two parts, the power stage circuit and the small signal control circuit. The power stage circuit contains components used to transmit large currents. Generally, these components should be placed first, and then small-signal control circuits should be placed at specific points in the layout.

High-current traces should be short and wide to minimize PCB inductance, resistance, and voltage drop. For those traces with high di/dt pulse currents, this aspect is especially important.

a shows the PCB parasitic inductance in the high di/dt current path. Due to the parasitic inductance, the pulse current path not only radiates magnetic fields, but also generates large voltage ringing and spikes on PCB traces and MOSFETs. In order to minimize the PCB inductance, the pulse current loop (the so-called thermal loop) should have the smallest circumference when laying out, and its trace should be short and wide.

High frequency decoupling capacitor CHF should be 0.1μF~10μF, X5R or X7R dielectric ceramic capacitor, it has very low ESL (effective series inductance) and ESR (equivalent series resistance). Larger capacitor dielectrics (such as Y5V) may cause the capacitance value to drop significantly at different voltages and temperatures, so it is not the best material for CHF.

b Provides a layout example for the key pulse current loop in a buck converter. In order to limit the resistance voltage drop and the number of vias, the power components are placed on the same side of the circuit board, and the power traces are also placed on the same layer. When it is necessary to route a certain power line to another layer, choose a line in the continuous current path. When using vias to connect the PCB layer in a high-current loop, use multiple vias to minimize impedance.