PCB Tech - PCB design guidelines to ensure signal integrity

The following is an introduction to PCB design guidelines to ensure signal integrity and resolve signals:

(SI) The earlier the problem, the higher the design efficiency, thus avoiding adding terminal equipment before the PCB design is completed.

There are many tools and resources for SI design planning. This article discusses the core issues of signal integrity and several methods to solve SI problems, while ignoring the technical details of the design process. 1 SI problem As the switching speed of IC output increases, almost all designs encounter signal integrity problems regardless of the signal period.

The circuit board can be completely grounded and easy to form a power loop, and a large number of discrete terminal devices can be used as needed, but the design must be correct and cannot be in a critical state. SI and EMC experts perform simulations and calculations before wiring, and then the circuit board design follows a series of very strict design rules. If in doubt, termination equipment can be added to obtain as much SI safety margin as possible. In the actual working process of the circuit board, there will always be some problems. Therefore, by using the controllable impedance terminal wiring, the SI problem can be avoided.

In short, the ultra-standard design solves the SI problem.

The following describes common SI design guidelines for the design process. 2 The pre-design preparation work before the start of the design must first consider and determine the design strategy to guide component selection, process selection and circuit board production cost control. In the case of SI, conduct pre-research to form planning or design guidelines to ensure that there are no obvious SI issues, crosstalk or timing issues in the design results. IC manufacturers can provide some design guidelines, but the guidelines provided by the chip supplier (or your own design guidelines) have limitations. According to the guidelines, the circuit board that meets the SI requirements may not be designed at all.

If the design rules are simple, no PCB design engineer is needed.

Before the actual PCB layout, the following problems need to be solved first. These problems will affect the circuit board you are designing (or considering designing) in most cases. If the number of circuit boards is large, this is very valuable. 3 cascaded circuit boards Some project groups have great autonomy in determining the number of PCB layers, while other project groups do not, so it is very important to know their position. Communicating with manufacturing and cost analysis engineers can determine the cascading error of the circuit board, which is also a good opportunity to discover the manufacturing tolerance of the circuit board.

All this information can be used in the pre-wiring phase. Based on the above data, you can choose to cascade. Please note that almost every PCB inserted into another circuit board or backplane has thickness requirements, and most circuit board manufacturers have fixed thickness requirements for the different types of layers they can manufacture, which will greatly limit the final level The number of joints. You may want to work closely with the manufacturer to define the number of cascades.

The impedance control tool should be used to generate the target impedance range of different layers, while considering the manufacturing tolerance provided by the manufacturer and the influence of adjacent wiring. Ideally, for signal integrity, all high-speed nodes should be connected to the impedance control inner layer (for example, stripline), but in reality, engineers must often use the outer layer to achieve the use of all or part of the high-speed nodes. In order to optimize the SI and keep the circuit board decoupled, the ground/power planes should be placed in pairs as much as possible. If you can only have a pair of ground/power planes, you will be there. If there is no power plane at all, you may encounter SI problems by definition.

Before defining the return path for undefined signals, you may also encounter situations where it is difficult to simulate or simulate the performance of the circuit board. 4Crosstalk and impedance control Coupling from adjacent signal lines will cause crosstalk and change the impedance of the signal line. The coupling analysis of adjacent parallel signal lines can determine the "safe" or expected spacing (or parallel wiring length) between signal lines or between various signal lines. For example, to limit the crosstalk between clock and data signal nodes to 100mV, but to keep the signal lines parallel, you can calculate or simulate to find the minimum allowable spacing between signals on any given wiring layer. At the same time, if the design includes nodes that are important to impedance (or clocks or dedicated high-speed memory architectures), routing must be placed on one layer (or multiple layers) to obtain the required impedance. 5 Important high-speed node delays and time lags It is a key factor that must be considered for clock routing. Due to strict timing requirements, the node usually must use terminal equipment to achieve the best SI quality.

To identify these nodes in advance, plan the time required to adjust the placement and routing of components in order to adjust the pointer to the signal integrity design. 6. The choice of PCB technology and different drive technology is suitable for different tasks. Is the signal point-to-point or slightly more? Is the signal output from the circuit board or is it left on the same circuit board? What is the allowable time delay and noise tolerance? As a general standard for signal integrity design, the slower the conversion speed, the better the signal integrity. There is no reason for a 50MHZ clock to use a 500PS rise time.

The 2-3NS swing frequency control device is fast enough to ensure the quality of SI and help solve the problems of synchronous output switching (SSO) and electromagnetic compatibility (EMC). In the new FPGA programmable technology or user-defined ASIC, the superiority of the drive technology can be found. With these custom (or semi-customizable) devices, you can have a lot of room to choose drive amplitude and speed.

At the beginning of the design, meet the FPGA (or ASIC) design time requirements and determine the appropriate output options, including pin selection (if possible). In this design stage, a suitable simulation model is obtained from the IC supplier.

In order to effectively cover the SI simulation, you will need a SI simulator and a corresponding simulation model (probably an IBIS model).

Finally, in the pre-wiring and routing stage, you should establish a series of design guidelines, including: target layer impedance, wiring spacing, preferred device technology, key node topology and termination planning.

7 The basic process of pre-wiring in the pre-wiring stage SI programming must first define the range of input parameters (drive amplitude, impedance, tracking speed) and possible topological range (minimum/maximum length, short length, etc.), and then run each possible simulation Combine, analyze the timing and SI simulation results, and finally find an acceptable value range. Next, the working range is interpreted as the wiring constraints of the PCB wiring. Different software tools can be used to perform this type of "cleanup" preparation, and the wiring program can automatically handle this wiring constraint.

SI simulation check after wiring will allow systematic destruction (or change) of design rules, but this is only necessary for cost considerations or strict wiring requirements. 9. The above measures can ensure the quality of the SI design of the circuit board. After the circuit board is assembled, it is still necessary to place the circuit board on the test platform, use an oscilloscope or TDR (time domain reflector) to measure, and compare the actual PCB board with the expected result of the simulation Compare. There are many articles about model selection. Engineers performing static timing verification may have noticed that although all the data can be obtained from the device data sheet, it is still difficult to build a model. In contrast to the SI simulation model, the model is easy to construct, but the model data is difficult to obtain. Essentially, the only reliable source of SI model data is the IC supplier, who must maintain a tacit cooperation with the design engineer. The IBIS model standard provides a consistent data carrier, but the establishment of the IBIS model and its quality assurance are costly. IC suppliers still need to promote the market demand for this investment, and the PCB manufacturer may be the only one and the market.