2022-08-30

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Author：iPCB

If you read many **PCB board**design guides, especially those on parallel protocols and differential pair routing, you will see a lot about trace length matching. When you need trace length matching, your goal is to minimize differential pairs in serial protocols, multiple pairs in parallel protocols (eg PCIe), multiple traces/pairs in parallel protocols or use the following protocols The timing differences between any protocols are source synchronous clocks. CAD tools make it easy to think about what's going on. However, what happens at other frequencies? More specifically, what happens to wideband signals? All digital signals are broadband signals whose frequency content extends from DC to infinity. Due to the large bandwidth of digital signals, which frequency should be used for trace length matching? Unfortunately, the frequency used for trace length matching is ambiguous, so designers need to understand how to deal with PCB board trace length matching versus frequency. To better understand this, we need to examine the techniques used in the wideband design and how the entire signal bandwidth is considered in trace length matching.

The relationship between PCB trace length matching and frequency of differential pair

Properly matching trace length to frequency requires consideration of the entire bandwidth of the signal propagating on the trace. This has been the subject of research in differential serial protocols over the past few years, with standards such as USB4 placing specific requirements on wideband signal integrity metrics. Some example wideband signal integrity metrics are:

Integrated differential crosstalk

Integral Differential Insertion Loss

Integral Differential Return Loss

Integral Differential Impedance Deviation

By "integrated", we mean that a particular aspect of signal integrity applies over the entire frequency range of interest. In other words, if we take differential crosstalk as an example, we want to reduce the differential crosstalk between two differential pairs below a certain limit, which is specified in the signaling standard. We'll see in a moment why this is important for tracking length matching.

Dispersion

In the time domain, we are only concerned with the halfway transition between the HI and LOW states (assuming binary) at the same instant at which both ends of the differential pair cross. Obviously, jitter creates a problem here, which is that it will limit your trace length to a certain tolerance, so you will never have a perfect transition on both ends of a pair of wires at the same time. In the frequency domain, we need to consider the following dispersion:

Geometric dispersion: This is due to the boundary conditions and geometry of the interconnect, which then determines how the impedance of the interconnect varies with geometry.

Dielectric Diffusion: This occurs in the PCB board substrate and is independent of the geometry of the interconnects on the PCB board. It includes dispersion and loss of DK.

Roughness Dispersion: This additional dispersion occurs due to causality in the copper roughness model and the skin effect at high frequencies.

Fiber Weave Dispersion: Fiber weave in PCB board laminates produces periodic dispersion changes throughout the interconnect.

Because these sources of dispersion are always present in the traces, they cause the impedance, speed, and all other signal integrity metrics of the actual PCB traces to be a function of frequency.

Signal speed

If you are familiar with transmission line theory, then you know that impedance and signal speed are closely related. Let's take the signal speed of a PCB board trace as an example. The figure below shows the group and phase velocities of a simulated stripline with roughness and dispersion. Group and phase velocities of signals on an example stripline with copper roughness and dielectric dispersion. Here we can see that the phase velocity varies greatly over a wide frequency range, from 1MHz to 20GHz by a factor of 2. The change in phase velocity is an important parameter here since this is the rate at which different frequency components propagate along the interconnect. With this change, we can see how difficult it becomes to match the length of the PCB traces to the frequency for practical interconnects. We need some way to account for all frequencies, not just an arbitrarily chosen single frequency.

Broadband Length Matching vs. Frequency

To formulate a measure of length matching, we need to consider the allowable length deviation for a given signaling standard. We call this time bias tlim. The function k here is simply the propagation constant of the signal on the interconnect, which is also a function of frequency due to dispersion, depending on the length of the allowed timing variation. We can take a statistical approach to deal with allowed length mismatches using a method called the "Lp norm". Without going too deep into the math involved, just know that this measure is equivalent to calculating the RMS difference between a function and some mean that differs only by a constant. Therefore, this makes it an ideal mathematical tool to address variations between certain target design values and signal integrity metrics (impedance, impulse response attenuation/delay, crosstalk strength, etc.). Using the Lp norm, we can rewrite the allowable length mismatch in terms of some upper bound defined by the timing mismatch limit tlim, according to the length variation of the allowable timing variation.

When using wideband signal integrity metrics for PCB board design, the above equation can be considered a constraint: when sizing transmission lines, this may affect the difference between the ends of a differential pair or between any two traces in The total allowable length deviation. High-speed parallel protocol. The integral is easy to calculate as long as you know the propagation constant of the transmission line. This value can then be calculated using a field solver, an analytical model with standard transmission line geometry to calculate manually. Just to give some numbers to the calculations, if I use the phase velocities of the simulated stripline shown above, we see that there is a mismatch in the allowable lengths between two single-ended fully isolated traces in parallel if the allowed values The timing mismatch is 10ps for 2.07mm. Note that for 10ps, this is a large fraction of the edge rate of many high-speed digital signals. For the stripline I simulated above, this equals an allowable length mismatch of 1.3041mm. In summary, we have shown that using the Lp norm can reduce PCB board trace length matching versus frequency to a single metric. If you are a PCB board designer, you do not need to perform this calculation manually, you just need to use the correct **PCB board** routing toolset.