PCB Tech - Parasitic capacitance and inductance of vias and how to use vias

Parasitic capacitance and inductance of vias and how to use vias

The via itself has parasitic stray capacitance. If it is known that the diameter of the solder mask on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the PCB board substrate is ε, the parasitic capacitance of the via is approximately C=1.41εTD1/(D2-D1)
The main effect of the parasitic capacitance of the via hole on the circuit is to extend the rise time of the signal and reduce the speed of the circuit. For example, for a PCB with a thickness of 50 mils, if the diameter of the via pad is 20 mils (drilling diameter is 10 mils) and the diameter of the solder mask is 40 mils, the parasitic capacitance of the vias can be approximated by the above formula for
C=1.41*4.4*0.050*0.020*/(0.040-0.020)≈0.31pF

The rise time change caused by this part of the capacitance is roughly T10-90=2.2C(Z0/2)=2.2x0.31x(50/2)=17.05ps
It can be seen from these values that although the effect of slowing the rising edge caused by the parasitic capacitance of a single via is not very obvious, if the via is used multiple times in the wiring to switch between layers, multiple vias will be used. Consider carefully when designing. In actual design, the parasitic capacitance can be reduced by increasing the distance between the via and the copper-clad area (Anti-pad) or reducing the diameter of the plate.
Vias have parasitic capacitances as well as parasitic inductances. In the design of high-speed digital circuits, the damage caused by the parasitic inductance of the vias is often greater than the impact of the parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. The following empirical formula can be used to simply calculate the parasitic inductance of a via:
L=5.08h[1n(4h/d)+1] where L is the length of the via hole, h is the length of the via hole, and d is the diameter of the center hole. It can be seen from the formula that the diameter of the via has a small effect on the inductance, and the greatest effect on the inductance is the length of the via. Still using the above example, the inductance of the via can be calculated as L=5.08*0.050*[1n(4*0.050/0.010)+1]≈1.015nH
If the rise time of the signal is 1ns, then the equivalent impedance is XL=πL/T10-90≈3.19Ω. Such impedance can no longer be ignored when there is a high-frequency current passing through.

Note: The bypass capacitor needs to pass through two vias when connecting the power plane and the ground plane, so that the parasitic inductance of the vias will increase exponentially.
Through the above analysis of the parasitic characteristics of the vias, it can be seen that in the design of high-speed PCBs, seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of the vias, the following 6 points should be done as much as possible in the design.
1. Considering both cost and signal quality, choose a reasonable size via. If necessary, consider using vias of different sizes. For example, for power or ground vias, you can consider using a larger size to reduce impedance; for signal wiring, you can use a smaller via. Of course, as the size of the via is reduced, the corresponding cost will also increase.
2. The use of a thinner PCB is beneficial to reduce the two parasitic parameters of the via.
3. The signal wiring on the PCB should not be changed as much as possible, which means that unnecessary vias should not be used as much as possible.
4. The power and ground pins should be drilled nearby, and the lead between the via and the pin should be as short as possible. Consider drilling multiple vias in parallel to reduce the equivalent inductance.
5. Place some grounded vias near the vias of the signal layer changeover to provide the nearest loop for the signal. You can even place some redundant ground vias on the PCB.
6. For high-density high-speed PCBs, you can consider using micro vias.