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PCB Tech
How to reduce noise and electromagnetic interference in PCB design
PCB Tech
How to reduce noise and electromagnetic interference in PCB design

How to reduce noise and electromagnetic interference in PCB design


How to reduce noise and electromagnetic interference in PCB design
How much do you know about reducing noise and electromagnetic interference in PCB design?
(1) Low-speed chips can be used instead of high-speed chips. High-speed chips are used in key places.
(2) A resistor can be connected in series to reduce the jump rate of the upper and lower edges of the control circuit.
(3) Try to provide some form of damping for relays, etc.
(4) Use the lowest frequency clock that meets the system requirements.
(5) The clock generator is as close as possible to the device using the clock. The shell of the quartz crystal oscillator should be grounded.
(6) Enclose the clock area with a ground wire and keep the clock wire as short as possible.
(7) The I/O drive circuit is as close as possible to the edge of the printed board, and let it leave the printed board as soon as possible. The signal entering the printed board should be filtered, and the signal from the high-noise area should also be filtered. At the same time, a series of terminal resistors should be used to reduce signal reflection.
(8) The useless end of MCD should be connected to high, or grounded, or defined as the output end, and the end of the integrated circuit that should be connected to the power supply ground should be connected, and should not be left floating.

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(9) Do not leave the input terminal of the gate circuit that is not in use. The positive input terminal of the unused op amp is grounded, and the negative input terminal is connected to the output terminal.
(10) As far as possible for the printed board, use 45-fold lines instead of 90-fold lines to reduce the external emission and coupling of high-frequency signals.
(11) The printed board is partitioned according to frequency and current switching characteristics, and the noise components and non-noise components should be farther apart.
(12) Use single-point power and single-point grounding for single and double panels. The power line and ground line should be as thick as possible. If the economy is affordable, use a multilayer board to reduce the capacitive inductance of the power supply and ground.
(13) The clock, bus, and chip select signals should be far away from I/O lines and connectors.
(14) The analog voltage input line and reference voltage terminal should be as far away as possible from the digital circuit signal line, especially the clock.
(15) For A/D devices, the digital part and the analog part would rather be unified than crossed.
(16) The clock line perpendicular to the I/O line has less interference than the parallel I/O line, and the clock component pins are far away from the I/O cable.
(17) The component pins should be as short as possible, and the decoupling capacitor pins should be as short as possible.
(18) The key line should be as thick as possible, and protective ground should be added on both sides. The high-speed line should be short and straight.
(19) Lines sensitive to noise should not be parallel to high-current, high-speed switching lines.
(20) Do not route wires under the quartz crystal and under noise-sensitive devices.
(21) For weak signal circuits, do not form current loops around low-frequency circuits.
(22) Do not form a loop in the signal. If it is unavoidable, make the loop area as small as possible.
(23) One decoupling capacitor per integrated circuit. A small high-frequency bypass capacitor must be added to each electrolytic capacitor.
(24) Use large-capacity tantalum capacitors or ju-cool capacitors instead of electrolytic capacitors for circuit charging and discharging energy storage capacitors. When using tubular capacitors, the case should be grounded.